Field programmable gate arrays are application-specific integrated circuits (popularly known as "ASICs") that can be configured by the user to perform desired logic functions. In the devices of interest here, the configuration data is stored in static RAM cells and therefore volatile.
Generally speaking, there are two instances where an FPGA would be programmed. The first instance is when one is beginning from a cold start. In this case, there will be a power-on reset after which the device is devoid of data. The device may also lack configuration data if there has been a power disturbance causing the device's memory to fail.
The second instance is during normal operation, when the power is on and the device already contains a specific configuration. In this case, the user may desire to reprogram the device with the same or a different configuration. The reprogramming request will erase the existing configuration and the device is then reloaded.
To use an FPGA, one must first configure the device to achieve the desired logical arrangement. Internally, as the configuration data is received, the FPGA serializes the data, accepting the data and performing the configuration bit-by-bit.
One method of configuring an FPGA is known as the master serial mode. Here, one uses a special serial PROM specifically programmed (e.g., burned in with a PROM programmer) with the configuration data. The contents of the PROMs are customarily generated using development tools provided by the FPGA manufacturer. During the configuration operation, the FPGA reads in the PROM's contents bit by bit through the configuration data input. In the master serial mode, the timing and control signals of the configuration operation are controlled by the FPGA. This arrangement requires one PROM per FPGA. Where there are several devices, overall component cost and real estate requirements will increase.
Another method is known as the slave serial mode. It is similar to the netaster serial mode in that it uses the same control signals and also provides the configuration data to the FPGA one bit at a time. However, the FPGA no longer controls the operation. Instead, timing and control of signals during the configuration operation is performed by circuitry external to the FPGA.
Another technique of configuring FPGAs is the master parallel mode. As with the master serial mode, the FPGA controls the timing and control signals for the operation. However, the FPGA reads the configuration data from an 8-bit PROM one byte at a time instead of one bit at a time. Nevertheless, because the FPGA then serializes the data for internal utilization, this method of configuring the FPGA ultimately requires the same amount of time as the master serial mode.
Another scheme for configuring FPGAs is the peripheral mode. In this mode, a microprocessor extracts data from a PROM and writes it to a byte-wide I/O port or memory address channeled to the FPGA. The FPGA internally serializes the configuration data and signals the processor when it is ready for the next byte.
A commonly-used method for configuring multiple devices is to connect them in a daisy chain. The lead device in the chain may be configured in any of the four modes outlined above. It fetches or receives its-configuration data in serial or parallel fashion, as determined by the configuration mode, until its configuration memory is full. Then, the first device passes the succeeding data to the next device and so on. In this daisy chain configuration, the devices are programmed one at a time, greatly increasing the total time required to complete the configuration of all of the devices.
Ideally, a programming method would achieve the following goals. First, it would require minimum component cost. Second, the method would afford a low latency, i.e., minimal overall programming time. Third, the preferred way of configuring the FPGAs would have the lowest board real estate requirement.